As semiconductor fabrication technology continues to improve, sizes of electronic devices are reduced, and as such, the size and channel length of the planar channel transistor also decrease correspondingly. The planar channel transistor has been widely used in integrated circuits; however, the continuous decreasing of the size and channel length of the planar channel transistor results in a volatile interaction between the two doped regions and a carrier channel under the gate oxide layer such that the controlling ability of the conductive metal layer on the switching operation of the carrier channel is reduced, i.e., causing a so-called “short channel effect”, which impedes the functioning of the planar channel transistor.
To solve the above-mentioned problem, non-planar device structures, such as fin-type field effect transistors, are becoming increasingly attractive as device options because of their effective short channel characteristics. The FinFET is a type of transistor that has source and drain regions in contact with a channel region contained in a semiconductor fin. Nearly all FinFETs are fabricated as double-gate FETs with opposing first and second gate conductors on either sidewall of the fin.
A (110) crystal orientation surface is effective for channel hole mobility but poor for channel electron mobility, while the (100) crystal orientation channel surface is poor for channel hole mobility but effective for channel electron mobility. Thus, a (110) sidewall orientation is a preferred orientation for PMOS FinFETs and a (100) sidewall orientation is a preferred orientation for NMOS FinFETs. To provide preferred surface orientations for PMOS and NMOS FinFETs on the same substrate, conventional integrated circuit devices, such as SRAM devices, have NMOS and PMOS FinFETs with different channel crystal orientations laid out in a non-aligned fin layout. Adjacent fins of different conductivity types are generally rotated by 45 degrees to accommodate for the different crystal orientations of the substrate surfaces. Such mixed rotations require increases in layout area of an integrated circuit device and increases lithography difficulties.
This “Discussion of the Background” section is provided for background information only. The statements in this “Discussion of the Background” are not an admission that the subject matter disclosed in this “Discussion of the Background” section constitutes prior art to the present disclosure, and no part of this “Discussion of the Background” section may be used as an admission that any part of this application, including this “Discussion of the Background” section, constitutes prior art to the present disclosure.